PIC16C58B-04/SS【PDF 34/194 页】IC MCU OTP 2KX12 20SSOP

收藏本站

您好，
买卖IC网欢迎您。
请登录
免费注册

买卖IC网

Sheet目录3889

30页 31页 32页 33页 [34页]35页 36页 37页 38页

PIC18F2450/4450

2006 Microchip Technology Inc.

Advance Information

DS39760A-page 127

13.4

PWM Mode

In Pulse-Width Modulation (PWM) mode, the CCP1 pin

produces up to a 10-bit resolution PWM output.

Figure 13-3 shows a simplified block diagram of the

CCP module in PWM mode.

For a step-by-step procedure on how to set up the CCP

module for PWM operation, see Section 13.4.3

“Setup for PWM Operation”.

FIGURE 13-3:

SIMPLIFIED PWM BLOCK

DIAGRAM

A PWM output (Figure 13-4) has a time base (period)

and a time that the output stays high (duty cycle).

The frequency of the PWM is the inverse of the

period (1/period).

FIGURE 13-4:

PWM OUTPUT

13.4.1

PWM PERIOD

The PWM period is specified by writing to the PR2

following formula:

EQUATION 13-1:

PWM frequency is defined as 1/[PWM period].

When TMR2 is equal to PR2, the following three events

occur on the next increment cycle:

TMR2 is cleared

The CCP1 pin is set (exception: if PWM duty

cycle = 0%, the CCP1 pin will not be set)

The PWM duty cycle is latched from CCPR1L into

CCPR1H

13.4.2

PWM DUTY CYCLE

The PWM duty cycle is specified by writing to the

CCPR1L register and to the CCP1CON<5:4> bits. Up

to 10-bit resolution is available. The CCPR1L contains

the eight MSbs and the CCP1CON<5:4> bits contain

the two LSbs. This 10-bit value is represented by

CCPR1L:CCP1CON<5:4>. The following equation is

used to calculate the PWM duty cycle in time:

EQUATION 13-2:

CCPR1L and CCP1CON<5:4> can be written to at any

time, but the duty cycle value is not latched into

CCPR1H until after a match between PR2 and TMR2

occurs (i.e., the period is complete). In PWM mode,

CCPR1H is a read-only register.

CCPR1L

CCPR1H (Slave)

Comparator

TMR2

Comparator

PR2

(Note 1)

Duty Cycle Registers

CCP1CON<5:4>

Clear Timer,

CCP1 pin and

latch D.C.

Note 1: The 8-bit TMR2 value is concatenated with the 2-bit

internal Q clock, or 2 bits of the prescaler, to create

the 10-bit time base.

CCP1

Corresponding

TRIS bit

Output

Period

Duty Cycle

TMR2 = PR2

TMR2 = Duty Cycle

TMR2 = PR2

Note:

The Timer2 postscalers (see Section 12.0

“Timer2 Module”) are not used in the

determination of the PWM frequency. The

postscaler could be used to have a servo

update rate at a different frequency than

the PWM output.

PWM Period = [(PR2) + 1] 4 TOSC

(TMR2 Prescale Value)

PWM Duty Cycle = (CCPR1L:CCP1CON<5:4>)

TOSC (TMR2 Prescale Value)

发布紧急采购，3分钟左右您将得到回复。

采购需求

(若只采购一条型号，填写一行即可)

*型号	*数量	厂商	批号	封装

添加更多采购

采购需求

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

发布成功！您可以继续发布采购。也可以进入我的后台，查看报价

我的联系方式